1. Field of the invention
The present invention relates to a phase detector, and more specifically a digital phase detector suitable for use in a phase locked loop for a timing signal regeneration circuit.
2. Description of related art
Phase locked loops have been widely utilized in the field of telecommunication and electronic measurements. One recently dominant type of phase locked loop is composed of a digital phase detector and a charge pump. One typical digital phase detector has been disclosed in a Japanese book "PLL Application Circuits", page 49, published on Sept. 10, 1977 from Sogodenshishuppansha. This digital phase detector has a first input V for receiving an output of a voltage controlled oscillator and a second input R for receiving a reference signal, and operates to compare the first input V with the second input R both in phase and in frequency. When a phase of the first input V is in advance of that of the second input R or when a frequency of the first input V is higher than that of the second input R, the digital phase detector outputs a charge-down signal for decrease of an oscillation frequency of the voltage controlled oscillator. On the other hand, when the phase of the first input V is delayed from that of the second input R or when the frequency of the first input V is lower than that of the second input R, the digital phase detector outputs a charge-up signal for increase of the oscillation frequency of the voltage controlled oscillator.
In actual telecommunication, the phase locked loop is in many cases used to regenerate a timing signal from a received signal. In this case, an input signal supplied to the second input R for the reference signal is constituted of a bit train composed of "0" S and "1" S at random. Under this circumstance, there will frequently occur such a situation that the first input V and the second input R are simultaneously at a low level. In this situation, however, the conventional digital phase detector has been often encountered with a problem of outputting the charge-down signal to the charge pump although the synchronism has already been attained in phase and/or in frequency. As a result, the synchronized condition is broken. The reason for this is that when both the first and second inputs V and R of the conventional digital phase detector are "0" (zero) the conventional digital phase detector often outputs the charge-down signal.